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| a FEATURES Supports DOCSIS and EuroDOCSIS Standards for Reverse Path Transmission Systems Gain Programmable in 1 dB Steps over a 59 dB Range Low Distortion at 60 dBmV Output: -57.5 dBc SFDR at 21 MHz -54 dBc SFDR at 65 MHz Output Noise Level @ Minimum Gain 1.2 nV/Hz Maintains 300 Output Impedance TX-Enable and Transmit-Disable Condition Upper Bandwidth: 107 MHz (Full Gain Range) 5 V Supply Operation Supports SPI Interfaces APPLICATIONS DOCSIS and EuroDOCSIS Cable Modems CATV Set-Top Boxes CATV Telephony Modems Coaxial and Twisted Pair Line Driver VIN+ DIFF OR SINGLE INPUT AMP 5 V Upstream Cable Line Driver AD8328* FUNCTIONAL BLOCK DIAGRAM BYP AD8328 VOUT+ VERNIER ATTENUATION CORE POWER AMP VOUT- ZOUT DIFF = 300 VIN- 8 DECODE ZIN (SINGLE) = 800 ZIN (DIFF) = 1.6k 8 DATA LATCH 8 SHIFT REGISTER POWER-DOWN LOGIC RAMP GND DATEN SDATA CLK TXEN SLEEP GENERAL DESCRIPTION -50 -52 -54 DISTORTION - dBc -56 -58 -60 -62 -64 -66 -68 -70 5 VOUT = 60 dBmV @MAX GAIN, SECOND HARMONIC VOUT = 60dBmV @MAX GAIN, THIRD HARMONIC The AD8328 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8328 ideally suited for MCNS-DOCSIS and Euro-DOCSIS applications. The gain of the AD8328 is digitally controlled. An 8-bit serial word determines the desired output gain over a 59 dB range, resulting in gain changes of 1 dB/LSB. The AD8328 accepts a differential or single-ended input signal. The output is specified for driving a 75 load through a 2:1 transformer. Distortion performance of -53 dBc is achieved with an output level up to 60 dBmV at 65 MHz bandwidth over a wide temperature range. This device has a sleep mode function that reduces the quiescent current to 2.6 mA and a full power-down function that reduces power-down current to 20 A. The AD8328 is packaged in a low cost 20-lead LFCSP package and a 20-lead QSOP package. The AD8328 operates from a single 5 V supply and has an operational temperature range of -40C to +85C. 15 25 35 45 55 65 FREQUENCY - MHz Figure 1. Worst Harmonic Distortion vs. Frequency *Patent Pending REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 AD8328-SPECIFICATIONS The AD8328 is characterized using a 2:1 transformer at the device output.) 1 (TA = 25 C, VS = 5 V, RL = RIN = 75 , VIN (Differential) = 29 dBmV. Parameter INPUT CHARACTERISTICS Specified AC Voltage Input Resistance Input Capacitance GAIN CONTROL INTERFACE Voltage Gain Range Max Gain Min Gain Output Step Size Output Step Size Temperature Coefficient OUTPUT CHARACTERISTICS Bandwidth (-3 dB) Bandwidth Roll-Off 1 dB Compression Point2 Output Noise2 Max Gain Min Gain Transmit Disable Noise Figure2 Max Gain Differential Output Impedance OVERALL PERFORMANCE Second-Order Harmonic Distortion 4, 5 Conditions Output = 60 dBmV, Max Gain Single-Ended Input Differential Input Min Typ 29 800 1600 2 Max Unit dBmV pF Gain Code = 60 Dec Gain Code = 1 Dec TA = -40C to +85C 58 30.5 -28.5 0.6 59.0 31.5 -27.5 1.0 0.0005 60 32.5 -26.5 1.4 dB dB dB dB/LSB dB/C All Gain Codes (1-60 Decimal Codes) f = 65 MHz Max Gain, f = 10 MHz, Output Referred Min Gain, f = 10 MHz, Input Referred f = 10 MHz f = 10 MHz f = 10 MHz f = 10 MHz TX Enable and TX Disable 17.9 2.2 107 1.2 18.4 3.3 135 1.2 1.1 16.7 75 30%3 151 1.3 1.2 17.7 MHz dB dBm dBm nV/Hz nV/Hz nV/Hz dB Third-Order Harmonic Distortion 4, 5 ACPR2, 6 Isolation (Transmit Disable) 2 POWER CONTROL TX Enable Settling Time TX Disable Settling Time Output Switching Transients 2 Output Settling Due to Gain Change Due to Input Step Change POWER SUPPLY Operating Range Quiescent Current f = 33 MHz, VOUT = 60 dBmV @ Max Gain f = 65 MHz, VOUT = 60 dBmV @ Max Gain f = 21 MHz, VOUT = 60 dBmV @ Max Gain f = 65 MHz, VOUT = 60 dBmV @ Max Gain Max Gain, f = 65 MHz Max Gain, VIN = 0 Max Gain, VIN = 0 Equivalent Output = 31 dBmV Equivalent Output = 61 dBmV Min to Max Gain Max Gain, VIN = 29 dBmV 4.75 98 18 1 1 -40 -67 -61 -57.5 -54 -58 -85 2.5 3.8 2.5 16 60 30 5 120 26 2.6 20 -56 -55 -56 -52.5 -56 -81 dBc dBc dBc dBc dBc dB s s mV p-p mV p-p ns ns 6 54 Max Gain Min Gain Transmit Disable (TXEN = 0) SLEEP Mode (Power-Down) 5.25 140 34 3.5 100 +85 V mA mA mA A C OPERATING TEMPERATURE RANGE NOTES 1 TOKO 458PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz. 2 Guaranteed by design and characterization to 4 sigma for T A = 25C. 3 Measured through a 2:1 transformer. 4 Specification is worst case over all gain codes. 5 Guaranteed by design and characterization to 3 sigma for T A = 25C. 6 VIN = 29 dBmV, QPSK modulation, 160 KSPS symbol rate. -2- REV. 0 AD8328 LOGIC INPUTS (TTL/CMOS Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, V Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current (VINH = 5 V) CLK, SDATA, DATEN Logic 0 Current (VINL = 0 V) CLK, SDATA, DATEN Logic 1 Current (VINH = 5 V) TXEN Logic 0 Current (VINL = 0 V) TXEN Logic 1 Current (VINH = 5 V) SLEEP Logic 0 Current (VINL = 0 V) SLEEP Specifications subject to change without notice. CC = 5 V. Full Temperature Range.) Min 2.1 0 0 -600 50 -250 50 -250 Typ Max 5.0 0.8 20 -100 190 -30 190 -30 Unit V V nA nA A A A A TIMING REQUIREMENTS (Full Temperature Range, V Parameter Clock Pulsewidth (tWH) Clock Period (tC) Setup Time SDATA vs. Clock (tDS) Setup Time DATEN vs. Clock (tES) Hold Time SDATA vs. Clock (tDH) Hold Time DATEN vs. Clock (tEH) Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF) Specifications subject to change without notice. t DS SDATA VALID DATA-WORD G1 MSB. . . .LSB CC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.) Min 16.0 32.0 5.0 15.0 5.0 3.0 10 Typ Max Unit ns ns ns ns ns ns ns VALID DATA-WORD G2 tC t WH CLK t ES DATEN t EH 8 CLOCK CYCLES GAIN TRANSFER (G1) GAIN TRANSFER (G2) t OFF TXEN t GS t ON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB MSB-1 MSB-2 t DS t DH CLK REV. 0 Figure 3. SDATA Timing -3- AD8328 ABSOLUTE MAXIMUM RATINGS* Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltage VIN+, VIN- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V p-p DATEN, SDATA, CLK, SLEEP, TXEN . . . . . . . . . . . . . . . . . . . . -0.8 V to +5.5 V Internal Power Dissipation QSOP, LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering 60 seconds . . . . . . . . . . 300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATIONS 20-Lead 20-Lead QSOP LFCSP GND VCC VCC GND 1 VCC 2 20 GND 19 VCC 18 TXEN GND 3 GND 4 20 19 18 17 16 GND 1 GND 2 VIN+ 3 VIN- 4 GND 5 6 DATEN GND TXEN TOP VIEW VIN- 6 (Not to Scale) 15 VOUT- GND 7 DATEN 8 14 BYP 13 NC VIN+ 5 AD8328 17 RAMP 16 VOUT+ 15 RAMP AD8328 TOP VIEW (Not to Scale) 14 VOUT+ 13 VOUT- 12 BYP 11 NC SDATA 9 CLK 10 12 SLEEP 11 GND 7 SDATA 8 CLK 9 GND 10 SLEEP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. 20-Lead LFCSP Pin No. 20-Lead QSOP Mnemonic GND VCC VIN+ VIN- DATEN Description Common External Ground Reference Common Positive External Supply Voltage. A 0.1 F capacitor must decouple each pin. Noninverting Input. DC-biased to approximately V CC/2. Should be ac-coupled with a 0.1 F capacitor. Inverting Input. DC-biased to approximately V CC/2. Should be ac-coupled with a 0.1 F capacitor. Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (most significant bit) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. Low Power Sleep Mode. In the Sleep mode, the AD8328's supply current is reduced to 20 A. A Logic 0 powers down the part (High ZOUT State), and a Logic 1 powers up the part. Internal Bypass. This pin must be externally ac-coupled (0.1 F capacitor). Negative Output Signal Positive Output Signal External RAMP Capacitor (optional) Logic 0 disables forward transmission. Logic 1 enables forward transmission. ORDERING GUIDE 1 ,2, 5, 1, 3, 4, 7, 9, 18, 19 11, 20 17, 20 3 4 6 2, 19 5 6 8 7 8 9 10 SDATA CLK 10 12 13 14 15 16 12 14 15 16 17 18 SLEEP BYP VOUT- VOUT+ RAMP TXEN Model AD8328ARQ AD8328ARQ-REEL AD8328ARQ-EVAL AD8328ACP AD8328ACP-REEL AD8328ACP-EVAL 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 20-Lead QSOP 20-Lead QSOP Evaluation Board 20-Lead LFCSP 20-Lead LFCSP Evaluation Board JA 83.2C/W 83.2C/W1 30.4C/W2 30.4C/W2 1 Package Option RQ-20 RQ-20 CP-20 CP-20 Thermal Resistance measured on SEMI standard 4-layer board. Thermal Resistance measured on SEMI standard 4-layer board, paddle soldered to board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8328 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. 0 Typical Performance Characteristics-AD8328 55 50 VOUT = 61dBmV @MAX GAIN VOUT = 60dBmV @MAX GAIN 60 DISTORTION - dBc 55 VOUT = 61dbmV @MAX GAIN 65 DISTORTION - dBc VOUT = 60dbmV @MAX GAIN 60 VOUT = 59dBmV @MAX GAIN 65 70 VOUT = 59dbmV @MAX GAIN 75 5 15 35 45 25 FREQUENCY - MHz 55 65 70 5 15 35 45 25 FREQUENCY - MHz 55 65 TPC 1. Second-Order Harmonic Distortion vs. Frequency for Various Output Powers -50 VOUT = 60dBmV @ MAX GAIN -55 DISTORTION - dBc TPC 4. Third-Order Harmonic Distortion vs. Frequency for Various Output Powers -50 VOUT = 60dBmV @ MAX GAIN TA = +85 C TA = +25 C TA = -40 C DISTORTION - dBc -55 -60 TA = +25 C -65 TA = -40 C -60 -70 TA = +85 C -75 -65 5 15 25 35 45 55 65 5 15 FREQUENCY - MHz 25 35 45 FREQUENCY - MHz 55 65 TPC 2. Second-Order Harmonic Distortion vs. Frequency vs. Temperature 10 0 -10 -20 -30 -40 -50 -60 -70 C0 C0 TPC 5. Third-Order Harmonic Distortion vs. Frequency vs. Temperature 60 VOUT = 57dBmV/TONE 50 @ MAX GAIN 40 30 CH PWR ACP 60dBmV -58.2dB VOUT - dBmV c11 c11 cu1 cu1 POUT - dBm 20 10 0 -10 -20 -30 -40 41.6 41.7 41.8 41.9 42 42.1 42.2 FREQUENCY - MHz 42.3 42.4 42.5 -80 -90 75kHz/DIV SPAN 750kHz TPC 3. Adjacent Channel Power TPC 6. Two-Tone Intermodulation Distortion REV. 0 -5- AD8328 40.0 30.0 20.0 10.0 0 DEC60 DEC54 0 10 20 30 TXEN = 0 VIN = 29dBmV GAIN - dB DEC48 DEC42 DEC36 ISOLATION - dB 40 50 60 70 80 MAX GAIN MIN GAIN -10.0 DEC30 DEC24 -20.0 -30.0 DEC18 DEC12 DEC 1 TO DEC 6 -40.0 0.1 1 10 FREQUENCY - MHz 100 1000 90 100 1 10 100 FREQUENCY - MHz 1000 TPC 7. AC Response TPC 10. Isolation in Transmit Disable Mode vs. Frequency 1.6 1.4 f = 10MHz 1.2 0.8 OUTPUT STEP SIZE - dB 1.2 GAIN ERROR - dB 0.4 0 0.4 f = 10MHz f = 5MHz f = 42MHz 1.0 0.8 0.8 1.2 f = 65MHz 0.6 0 6 12 18 24 30 36 42 48 GAIN CONTROL - Decimal Code 54 60 1.6 0 6 12 18 24 30 36 42 48 GAIN CONTROL - Decimal Code 54 60 TPC 8. Output Step Size vs. Gain Control TPC 11. Gain Error vs. Gain Control 140 OUTPUT REFERRED VOLTAGE NOISE - nV/ Hz 130 f = 10MHz TXEN = 1 120 100 QUIESCENT SUPPLY CURRENT - mA 120 110 100 90 80 70 60 50 40 30 80 60 40 20 0 0 6 12 18 24 30 36 42 48 GAIN CONTROL - Decimal Code 54 60 20 0 10 20 30 40 GAIN CONTROL - Decimal Code 50 60 TPC 9. Output Referred Voltage Noise vs. Gain Control TPC 12. Supply Current vs. Gain Control -6- REV. 0 AD8328 5V signals in the preamp and DAC gain blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output stage. The output stage maintains 300 differential output impedance, which maintains proper match to 75 when used with a 2:1 balun transformer. SPI Programming and Gain Adjustment VOUT+ RL VOUT- VCC VIN+ AD8328 VIN- 1 2 1 2 VIN VIN BYP GND Figure 4. Characterization Circuit APPLICATIONS General Applications The AD8328 is primarily intended for use as the power amplifier (PA) in DOCSIS (Data Over Cable Service Interface Specification) certified cable modems and CATV set-top boxes. The upstream signal is either a QPSK or QAM signal generated by a DSP, a dedicated QPSK/QAM modulator, or a DAC. In all cases, the signal must be low-pass filtered before being applied to the PA in order to filter out-of-band noise and higher order harmonics from the amplified signal. Due to the varying distances between the cable modem and the head-end, the upstream PA must be capable of varying the output power by applying gain or attenuation. The ability to vary the output power of the AD8328 ensures that the signal from the cable modem will have the proper level once it arrives at the head-end. The upstream signal path commonly includes a diplexer and cable splitters. The AD8328 has been designed to overcome losses associated with these passive components in the upstream cable path. Circuit Description The AD8328 is controlled through a serial peripheral interface (SPI) of three digital data lines: CLK, DATEN, and SDATA. Changing the gain requires eight bits of data to be streamed into the SDATA port. The sequence of loading the SDATA register begins on the falling edge of the DATEN pin, which activates the CLK line. With the CLK line activated, data on the SDATA line is clocked into the serial shift register on the rising edge of the CLK pulses, most significant bit (MSB) first. The 8-bit data-word is latched into the attenuator core on the rising edge of the DATEN line. This provides control over the changes in the output signal level. The serial interface timing for the AD8328 is shown in Figures 2 and 3. The programmable gain range of the AD8328 is -28 dB to +31 dB with steps of 1 dB per least significant bit (LSB). This provides a total gain range of 59 dB. The AD8328 was characterized with a differential signal on the input and a TOKO 458PT-1087 2:1 transformer on the output. The AD8328 incorporates supply current scaling with gain code, as seen in TPC 12. This allows reduced power consumption when operating in lower gain codes. Input Bias, Impedance, and Termination The VIN+ and VIN- inputs have a dc bias level of VCC/2; therefore the input signal should be ac-coupled as seen in the typical application circuit (see Figure 5). The differential input impedance of the AD8328 is approximately 1.6 k, while the single-ended input is 800 . The high input impedance of the AD8328 allows flexibility in termination and properly matching filter networks. The AD8328 will exhibit optimum performance when driven with a pure differential signal. Output Bias, Impedance, and Termination The AD8328 is composed of three analog functions in the power-up or forward mode. The input amplifier (preamp) can be used single-ended or differentially. If the input is used in the differential configuration, it is imperative that the input signals be 180 degrees out of phase and of equal amplitude. A vernier is used in the input stage for controlling the fine 1 dB gain steps. This stage then drives a DAC, which provides the bulk of the AD8328's attenuation. The VCC 10 F The output stage of the AD8328 requires a bias of +5 V. The +5 V power supply should be connected to the center tap of the output transformer. Also, the VCC that is being applied to the center tap of the transformer should be decoupled as seen in the typical applications circuit (Figure 5). 0.1 F VIN+ ZIN = 150 165 0.1 F VIN- 1 20 QSOP GND GND 2 19 VCC VCC 3 18 TXEN GND 4 17 RAMP GND 5 16 VOUT+ VIN+ 6 15 VOUT- VIN- 7 14 BYP GND 13 8 0.1 F NC DATEN 12 9 SLEEP SDATA 11 10 GND CLK AD8328 0.1 F TO DIPLEXER ZIN = 75 TOKO 458PT-1087 0.1 F DATEN SDATA CLK TXEN SLEEP 1k 1k 1k 1k 1k Figure 5. Typical Application Circuit REV. 0 -7- AD8328 Table I. Adjacent Channel Power Adjacent Channel Symbol Rate (kSym/s) Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120 160 -58 -58 -60 -62 -64 -66 320 -60 -59 -58 -60 -62 -65 640 -63 -60 -59 -59 -60 -62 1280 -66 -64 -61 -60 -59 -61 2560 -66 -66 -64 -61 -60 -59 5120 -64 -65 -65 -63 -61 -60 The output impedance of the AD8328 is 300 , regardless of whether the amplifier is in transmit enable or transmit disable mode. This, when combined with a 2:1 voltage ratio (4:1 impedance ratio) transformer, eliminates the need for external back termination resistors. If the output signal is being evaluated using standard 50 test equipment, a minimum loss 75 -50 pad must be used to provide the test circuit with the proper impedance match. The AD8328 evaluation board provides a convenient means to implement a matching attenuator. Soldering a 43.3 resistor in the R15 placeholder and an 86.6 resistor in the R16 placeholder will allow testing on a 50 system. When using a matching attenuator, it should be noted that there will be a 5.7 dB of power loss (7.5 dB voltage) through the network. Power Supply and Gain Adjustment section. The TXEN pin can then be brought from Logic 0 to Logic 1, enabling forward signal transmission at the desired gain level. RAMP Pin and BYP Pin Features The RAMP pin (Pin 15) is used to control the length of the burst on and off transients. By default, leaving the RAMP pin unconnected will result in a transient that is fully compliant with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During Burst On/Off Transients. DOCSIS requires that all between burst transients must be dissipated no faster than 2 s. Adding capacitance to the RAMP pin will add more time to the transient. The BYP pin is used to decouple the output stage at midsupply. Typically, for normal DOCSIS operation, the BYP pin should be decoupled to ground with a 0.1 F capacitor. However, in applications that may require transient on/off times faster than 2 s, smaller capacitors may be used, but it should be noted that the BYP pin should always be decoupled to ground. Transmit Enable (TXEN) and SLEEP The 5 V supply should be delivered to each of the VCC pins via a low impedance power bus to ensure that each pin is at the same potential. The power bus should be decoupled to ground using a 10 F tantalum capacitor located close to the AD8328. In addition to the 10 F capacitor, each VCC pin should be individually decoupled to ground with ceramic chip capacitors located close to the pins. The bypass pin, labeled BYP, should also be decoupled. The PCB should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the AD8328 and the output transformer. All AD8328 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes. Signal Integrity Layout Considerations Careful attention to printed circuit board layout details will prevent problems due to board parasitics. Proper RF design techniques are mandatory. The differential input and output traces should be kept as short as possible. Keeping the traces short will minimize parasitic capacitance and inductance. This is most critical between the outputs of the AD8328 and the 2:1 output transformer. It is also critical that all differential signal paths be symmetrical in length and width. In addition, the input and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. Following these guidelines will optimize the overall performance of the AD8328 in all applications. Initial Power-Up The asynchronous TXEN pin is used to place the AD8328 into between-burst mode. In this reduced current state, the output impedance of 75 is maintained. Applying Logic 0 to the TXEN pin deactivates the on-chip amplifier, providing a 97.8% reduction in consumed power. For 5 V operation, the supply current is typically reduced from 120 mA to 2.6 mA. In this mode of operation, between-burst noise is minimized and high input to output isolation is achieved. In addition to the TXEN pin, the AD8328 also incorporates an asynchronous SLEEP pin, which may be used to further reduce the supply current to approximately 20 A. Applying Logic 0 to the SLEEP pin places the amplifier into SLEEP mode. Transitioning into or out of SLEEP mode may result in a transient voltage at the output of the amplifier. Distortion, Adjacent Channel Power, and DOCSIS When the supply voltage is first applied to the AD8328, the gain of the amplifier is initially set to gain code 1. As power is first applied to the amplifier, the TXEN pin should be held low (Logic 0) to prevent forward signal transmission. After power has been applied to the amplifier, the gain can be set to the desired level by following the procedure provided in the SPI Programming -8- To deliver the DOCSIS required 58 dBmV of QPSK signal and 55 dBmV of 16 QAM signal, the PA is required to deliver up to 60 dBmV. This added power is required to compensate for losses associated with the diplex filter or other passive components that may be included in the upstream path of cable modems or set-top boxes. It should be noted that the AD8328 was characterized with a differential input signal. TPCs 1 and 4 show the AD8328 second and third harmonic distortion performance versus the fundamental frequency for various output power levels. These figures are useful for determining the in-band harmonic levels from 5 MHz to 65 MHz. Harmonics higher in frequency (above 42 MHz for DOCSIS and above 65 MHz for EuroDOCSIS) will be sharply attenuated by the low-pass filter function of the diplexer. Another measure of signal integrity is adjacent channel power, commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1 REV. 0 AD8328 states, "Spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates." TPC 3 shows the measured ACP for a 60 dBmV QPSK signal taken at the output of the AD8328 evaluation board. The transmit channel width and adjacent channel width in TPC 3 correspond to the symbol rates of 160 kSym/s. Table I shows the ACP results for the AD8328 driving a QPSK, 60 dBmV signal for all conditions in DOCSIS Table 6-9, Adjacent Channel Spurious Emissions. Noise and DOCSIS Differential Signal from Single-Ended Source The default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. This configuration uses a 1:1 balun transformer to approximate a differential signal. Because of the nonideal nature of real transformers, the differential signal is not purely equal and opposite in amplitude. Although this circuit slightly sacrifices even order harmonic distortion due to asymmetry, it does provide a convenient way to evaluate the AD8328 with a single-ended source. The AD8328 evaluation board is populated with a TOKO 617DB-A0070 1:1 for this purpose (T1). Table II provides typical R4 values for common input configurations. Other input impedances may be calculated using the equation in Figure 7. Refer to Figure 10 for an evaluation board schematic. To utilize the transformer for converting a single-ended source into a differential signal, the input signal must be applied to VIN+. R4 = VIN ZIN R4 At minimum gain, the AD8328 output noise spectral density is 1.2 nV/Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious Emissions in 5 MHz to 42 MHz, specifies the output noise for various symbol rates. The calculated noise power in dBmV for 160 kSym/s is: 2 20 x log 1.2 nV x 160 kHz + 60 = - 66.4 dBmV Hz Comparing the computed noise power of -66.4 dBmV to the +8 dBmV signal yields -74.4 dBc, which meets the required level set forth in DOCSIS Table 6-10. As the AD8328 gain is increased above this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal-to-noise ratio that improves with gain. In transmit disable mode, the output noise spectral density is 1.1 nV/Hz, which results in -67 dBmV when computed over 160 kSym/s. The noise power was measured directly at the output of the AD8328AR-EVAL board. Evaluation Board Features and Operation Z IN x 1.6 k 1.6 k - Z IN AD8328 Figure 7. Single to Differential Circuit Single-Ended Source The AD8328 evaluation board and control software can be used to control the AD8328 upstream cable driver via the parallel port of a PC. A standard printer cable connected to the parallel port of the PC is used to feed all the necessary data to the AD8328 using the Windows(R)-based control software. This package provides a means of controlling the gain and the power mode of the AD8328. With this evaluation kit, the AD8328 can be evaluated in either a single-ended or differential input configuration. A schematic of the evaluation board is provided in Figure 11. Differential Signal Source Although the AD8328 was designed to have optimal DOCSIS performance when used with a differential input signal, the AD8328 may also be used as a single-ended receiver, or an IF digitally controlled amplifier. However, as with the single-ended to differential configuration noted above, even order harmonic distortion will be slightly degraded. When operating the AD8328 in a single-ended input mode, VIN+ and VIN- should be terminated as illustrated in Figure 8. On the AD8328 evaluation boards, this termination method requires the removal of R2 and R3 to be shorted with R4 open, as well as the addition of 82.5 at R1 and 39.2 at R17 for 75 termination. Table II shows the correct values for R11 and R12 for some common input configurations. Other input impedance configurations may be accommodated using the equations in Figure 8. R1 = Z IN x 800 Z x R1 R17 = IN 800 - Z IN R1 + Z IN Typical applications for the AD8328 use a differential input signal from a modulator or a DAC. See Table II for common values of R4, or calculate other input configurations using the equation in Figure 6. This circuit configuration will give optimal distortion results due to the symmetric input signals. It should be noted that this is the configuration that was used to characterize the AD8328. Z x 1.6 k R 4 = IN 1.6 k - Z IN VIN+ ZIN VIN- R4 VIN+ R1 ZIN R17 AD8328 AD8328 Figure 8. Single-Ended Circuit Figure 6. Differential Circuit REV. 0 -9- AD8328 Table II. Common Matching Resistors Controlling Gain/Attenuation of the AD8328 Differential Input Termination ZIN () 50 75 100 150 R2/R3 Open Open Open Open R4 () 51.1 78.7 107.0 165.0 R1/R17 Open/Open Open/Open Open/Open Open/Open The slide bar controls the gain/attenuation of the AD8328, which is displayed in dB and in V/V. The gain scales 1 dB per LSB. The gain code from the position of the slide bar is displayed in decimal, binary, and hexadecimal (Figure 10). Single-Ended Input Termination ZIN () 50 75 R2/R3 0 /0 0 /0 R4 () Open Open R1/R17 53.6 /25.5 82.5 /39.2 Overshoot on PC Printer Ports The data lines on some PC parallel printer ports have excessive overshoot that may cause communications problems when presented to the CLK pin of the AD8328. The evaluation board was designed to accommodate a series resistor and shunt capacitor (R2 and C5 in Figure 11) to filter the CLK signal if required. Installing Visual Basic Control Software - Install the CabDrive_28 software by running the setup.exe file on disk one of the AD8328 evaluation software. Follow the on-screen directions and insert disk two when prompted. Choose installation directory and then select the icon in the upper left to complete the installation. Running AD8328 Software Figure 10. Control Software Interface Transmit Enable and Sleep Mode To load the control software, go to START, PROGRAMS, CABDRIVE_28 or select the AD8328.exe file from the installed directory. Once loaded, select the proper parallel port to communicate with the AD8328 (Figure 9). The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8328 by asserting logic levels on the asynchronous TXEN pin. The Transmit Disable button applies Logic 0 to the TXEN pin, disabling forward transmission. The Transmit Enable button applies Logic 1 to the TXEN pin, enabling the AD8328 for forward transmission. Checking the Enable SLEEP Mode checkbox applies Logic 0 to the asynchronous SLEEP pin, setting the AD8328 for SLEEP mode. Memory Functions The Memory section of the software provides a way to alternate between two gain settings. The X->M1 button stores the current value of the gain slide bar into memory, while the RM1 button recalls the stored value, returning the gain slide bar to the stored level. The same applies to the X->M2 and RM2 buttons. Figure 9. Parallel Port Selection -10- REV. 0 AD8328 VIN _A R1 R2 T1 TOKO 617DB-A0070 VIN _A R17 R3 R4 78.7 C2A 0.1 F 1 2 3 C1A 0.1 F TP9 VCC C8 10 F GND VCC GND GND VIN+ VIN- GND DATEN SDATA CLK QSOP GND VCC TXEN RAMP VOUT+ VOUT- BYP NC SLEEP GND 20 19 18 17 16 15 14 13 12 11 C9 0.1 F C10 0.1 F TP1 P1 2 R5 1k C3 R6 0 4 5 6 7 8 C11 TOKO 458PT-1087 1 6 2 3 4 R15 0 CABLE_OA R16 C12 0.1 F VCC1 R7 1k P1 3 C4 TP2 R8 0 9 10 AD8328 C13 0.1 F TP3 P1 19 P1 20 P1 21 P1 22 P1 23 P1 24 P1 25 P1 26 P1 27 P1 28 P1 29 P1 30 P1 33 P1 5 R9 1k C5 R10 0 TP10 TP11 TP4 R12 0 C6 TP5 R14 0 C7 TP_AGND1 AGND1 TP12 R11 1k P1 6 TP_VCC1 VCC1 R13 1k P1 7 P1 16 Figure 11. AD8328 Evaluation Board Schematic REV. 0 -11- AD8328 Figure 12. Primary Side Figure 15. Internal Ground Plane Figure 13. Component Side Silkscreen Figure 16. Secondary Side Figure 14. Internal Power Plane Figure 17. Secondary Side Silkscreen -12- REV. 0 AD8328 OUTLINE DIMENSIONS 20-Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body (CP-20) Dimensions shown in millimeters 0.60 MAX 0.60 MAX PIN 1 INDICATOR TOP VIEW 4.0 BSC SQ 16 15 20 1 3.75 BSC SQ 0.75 0.55 0.35 11 10 BOTTOM VIEW 6 5 2.25 2.10 SQ 1.95 12 MAX 1.00 0.90 0.80 SEATING PLANE 0.50 BSC 0.70 MAX 0.65 NOM 0.05 0.02 0.00 0.30 0.23 0.18 COPLANARITY 0.08 0.25 REF COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS 20-Lead SOIC, 0.025 Lead Pitch [QSOP] (RQ-20) Dimensions shown in millimeters and (inches) 8.74 (0.3341) 8.56 (0.3370) 24 13 3.99 (0.1571) 3.81 (0.1500) 1 12 6.20 (0.2441) 5.79 (0.2280) PIN 1 1.50 (0.0591) MAX 0.30 (0.0118) 0.20 (0.0079) 1.75 (0.0689) 1.35 (0.0531) 0.25 (0.0098) 0.64 (0.0252) BSC 0.10 (0.0039) 8 0 SEATING 0.20 (0.0079) PLANE 0.18 (0.0071) 1.27 (0.0500) 0.41 (0.0161) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. 0 -13- -14- -15- -16- C03158-0-11/02(0) PRINTED IN U.S.A. This datasheet has been download from: www..com Datasheets for electronics components. |
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